1. Field
The present disclosure relates to techniques for singulating hybrid optical chips. More specifically, the present disclosure relates to techniques for singulating hybrid optical chips from a common wafer.
2. Related Art
Hybrid integration by flip-chip bonding is a practical approach for combining CMOS VLSI chips with non-CMOS components. Using this fabrication technique, each component may be built on its individually optimized technology platform. This approach can be used to accelerate the availability of the integrated component compared to the design and process integration efforts that would be required for monolithic integration (if such monolithic integration of the disparate technologies were even possible).
2.5D heterogeneous integration (which is sometimes referred to as ‘hybrid integration’) is a fabrication technique in which chips built on different technology platforms are juxtaposed on a common substrate, such as a silicon interposer. The surface mounted chips can be interconnected using high-density and high-bandwidth wiring on this common interposer.
A time- and cost-efficient approach for fabricating hybrid or 2.5D chips is a chip-on-wafer fabrication technique. In this fabrication technique, diced chips of one type are attached to chips of the second type that are still in wafer form. In the case of 2.5D heterogeneous integration, multiple diced chips may be attached to an interposer that is still in wafer form. In each case, singulation of the widget (e.g., the chip, the interposer, etc.), which is still in wafer form, may be performed after bonding to yield the assembled chip. In general, standard singulation process flows involving a dicing saw cut or laser ablation may be used, because even after the chip-on-wafer bonding, the dicing lanes between the chips are still clear and available.
As shown in FIG. 1, hybrid integrated photonic chips, such as bridge chips, are hybrid-integrated components that embody an electrical interface for local communications and optical access for global interconnections (via either optical fiber or optical waveguides on another routing layer). These bridge chips may be fabricated by attaching silicon photonic integrated circuits to a VLSI chip. Moreover, photonic bridge chips are typically assembled in diving-board configurations, such that at least one edge of the photonic integrated circuits is sufficiently exposed and hangs off an edge of the VLSI chip to provide access for surface-normal or edge-coupling optical input/output (I/O) circuits. Therefore, in a chip-on-wafer fabrication technique, where the chips being bonded to the target wafer (such as the active-CMOS or the passive-interposer substrate) include photonic integrated circuits that hang over the singulation boundary of the bottom chip/interposer, component singulation after bonding using an existing singulation process flow is usually not possible. This is because cutting along the dicing lanes on the wafer would also imply cutting through the photonic integrated circuits.
Hence, what is needed is a fabrication technique without the above-described problems.